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INTEGRATED CIRCUITS
DATA SHEET
PCD3350A 8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
Product specification Supersedes data of 1996 May 09 File under Integrated Circuits, IC03 1996 Dec 18
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
CONTENTS 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.4 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FREQUENCY GENERATOR Frequency generator derivative registers Melody output (P1.7/MDY) DTMF clock divider and output (DP1.7/DCO) Frequency registers DTMF frequencies Modem frequencies Musical scale frequencies EEPROM AND TIMER 2 ORGANIZATION EEPROM registers EEPROM latches EEPROM flags EEPROM macros EEPROM access Timer 2 REAL-TIME CLOCK Oscillator Divider chain Frequency adjustment Real-time clock derivative registers 9 10 11 12 13 14 15 16 17 18 19 20 21 21.1 21.2 21.3 21.4 22 23
PCD3350A
DERIVATIVE INTERRUPTS TIMING RESET IDLE MODE STOP MODE SUMMARY OF I/O PORTS AND ROM MASK OPTIONS SUMMARY OF DERIVATIVE REGISTERS HANDLING LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
1 FEATURES
PCD3350A
* 8-bit CPU, ROM, RAM, EEPROM, real-time clock and I/O; all in a 44-lead quad flat package * 8 kbytes ROM * 256 bytes RAM * 256 bytes Electrically Erasable Programmable Read Only Memory (EEPROM) * 32 kHz crystal oscillator for Real-Time Clock (RTC) * EEPROM programmable RTC * Over 100 instructions (based on MAB8048) all of 1 or 2 cycles * 34 quasi-bidirectional I/O port lines * 8-bit programmable Timer/event counter 1 * 8-bit reloadable Timer 2 * Three single-level vectored interrupts: - external - 8-bit programmable Timer/event counter 1 - derivative; triggered by reloadable Timer 2 * Two test inputs, one of which also serves as the external interrupt input * DTMF, modem, musical tone generator * Reference for supply and temperature-independent tone output * Filtering for low output distortion (CEPT compatible) * Melody output for ringer application * Programmable DTMF clock divider * Power-on-reset * Stop and Idle modes 3 ORDERING INFORMATION (see note 1)
* Supply voltage: 1.8 to 6 V (DTMF tone output and EEPROM erase/write from 2.5 V) * CPU clock frequency: 1 to 16 MHz (3.58 MHz or 10.74 MHz for DTMF) * Operating ambient temperature: -25 to +70 C * Manufactured in silicon gate CMOS process. 2 GENERAL DESCRIPTION
This data sheet details the specific properties of the PCD3350A. The shared properties of the PCD33xxA family of microcontrollers are described in the "PCD33xxA family" data sheet, which should be read in conjunction with this publication. The PCD3350A is a microcontroller designed primarily for telephony applications. It includes 8 kbytes ROM, 256 bytes RAM, 34 I/O lines, and an on-chip generator for dual tone multifrequency (DTMF), modem and musical tones. In addition to dialling, the generated frequencies can be made available as square waves for melody generation, providing ringer operation. The PCD3350A also incorporates 256 bytes of EEPROM, permitting data storage without battery backup. The EEPROM can be used for storing telephone numbers, particularly for implementing redial functions. Finally, the PCD3350A includes a low power 32 kHz crystal oscillator with an EEPROM programmable Real-Time Clock (RTC) working in standby mode. The instruction set is similar to that of the MAB8048 and is a sub-set of that listed in the "PCD33xxA family" data sheet.
PACKAGE TYPE NUMBER NAME PCD3350AH Note 1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and the ROM mask options. QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm VERSION SOT205-1
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4
handbook, full pagewidth
1996 Dec 18 BLOCK DIAGRAM
DP1.0 to DP1.7/DCO P0.0 to P0.7 8 6 DP0.0/RCO to DP0.5 8 fDTMF DER. PORT 1 BUFFER PORT 1 BUFFER 8 P1.0 to P1.7/MDY
Philips Semiconductors
P2.0 to P2.3
TONE
4
PORT 2 BUFFER
FILTER DER. PORT 1 FLIP-FLOP DECODE PORT 1 FLIP-FLOP PORT 0 FLIP-FLOP DER. PORT 0 FLIP-FLOP
PCD3350A
RESIDENT ROM 8 kbytes PORT 0 BUFFER DER. PORT 0 BUFFER
PORT 2 FLIP-FLOP
SINE WAVE GENERATOR
INTERNAL CLOCK FREQ. 30 MEMORY BANK FLIP-FLOPS 32 T1 8 8 5 8 8 8 8 8 TIMER/ EVENT COUNTER PROGRAM STATUS WORD HIGHER PROGRAM COUNTER LOWER PROGRAM COUNTER
HGF REGISTER
LGF REGISTER
DTMF-CLOCK & MELODY CONTROL REGISTER 8
4
8
8
6
8 8 8 8
8
8
8
8
8
8
8 8 8
8
8
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
4
INTERRUPT LOGIC ACCUMULATOR RAM ADDRESS REGISTER timer interrupt derivative interrupt ARITHMETIC TEMPORARY REGISTER 2 INSTRUCTION REGISTER AND DECODER TEMPORARY REGISTER 1 LOGIC UNIT T1 CE/T0 CONDITIONAL BRANCH LOGIC CONTROL AND TIMING CE/T0 RESET INITIALIZE XTAL1 INTERRUPT XTAL2 ACC ACC BIT TEST TIMER FLAG CARRY STOP IDLE DECIMAL ADJUST RTC interrupt D E C O D E external interrupt OSCILLATOR
TIMER 2 RELOAD REGISTER
TIMER 2 REGISTER
EEPROM CONTROL REGISTER
EEPROM ADDRESS REGISTER
EEPROM DATA TRANSFER
MULTIPLEXER
CLOCK CONTROL REGISTER
FREQUENCY ADJUSTMENT REGISTER
REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 8 LEVEL STACK (VARIABLE LENGTH) OPTIONAL SECOND REGISTER BANK
REAL-TIME CLOCK DIVIDER CHAIN
EEPROM 256 bytes
REAL-TIME CLOCK 32 kHz OSCILLATOR DATA STORE RTC1 RTC2
POWER-ON-RESET
VPOR
RESET
RESIDENT RAM ARRAY 256 bytes
MED263
Product specification
PCD3350A
Fig.1 Block diagram.
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
5 5.1 PINNING INFORMATION Pinning
PCD3350A
handbook, full pagewidth
43 P1.7/MDY
37 TONE
38 VDD
42 P1.6
34 P1.1
41 P1.5
35 P1.2
44 P2.0
40 P1.4
36 VSS
39 P1.3
P2.1 P2.2 P2.3 DP0.0/RCO DP0.1 DP0.2 DP0.3 DP0.4 DP0.5
1 2 3 4 5 6 7 8 9
33 P1.0 32 P0.7 31 P0.6 30 P0.5 29 P0.4
PCD3350AH
28 XTAL2 27 XTAL1 26 P0.3 25 P0.2 24 P0.1 23 P0.0
RTC1 10 RTC2 11
DP1.6 21
DP1.7/DCO 22
CE/T0 12
T1 13
RESET 14
DP1.0 15
DP1.1 16
DP1.2 17
DP1.3 18
DP1.4 19
DP1.5 20
MED264
Fig.2 Pin configuration.
1996 Dec 18
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Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
5.2 Pin description SOT205-1 package (for information on parallel I/O ports, see Chapter 14) PIN 1 to 3 4 5 to 9 10 11 12 13 14 15 to 21 22 23 to 26 27 28 29 to 32 33 to 35 36 37 38 39 to 42 43 44 TYPE I/O I/O I/O I O I I I I/O I/O I/O I O I/O I/O P O P I/O I/O I/O DESCRIPTION 3 bits of Port 2: 4-bit quasi-bidirectional I/O port
PCD3350A
Table 1
SYMBOL P2.1 to P2.3 DP0.0/RCO DP0.1 to DP0.5 RTC1 RTC2 CE/T0 T1 RESET DP1.0 to DP1.6 DP1.7/DCO P0.0 to P0.3 XTAL1 XTAL2 P0.4 to P0.7 P1.0 to P1.2 VSS TONE VDD P1.3 to P1.6 P1.7/MDY P2.0
1 bit of Derivative Port 0: 6-bit quasi-bidirectional I/O port; or RTC output 5 bits of Derivative Port 0: 6-bit quasi-bidirectional I/O port Real Time Clock 32 kHz oscillator input Real Time Clock 32 kHz oscillator output Chip Enable or Test 0 input Test 1/count input of 8-bit Timer/event counter 1 reset input 7 bits of Derivative Port 1: 8-bit quasi-bidirectional I/O port 1 bit of Derivative Port 1: 8-bit quasi-bidirectional I/O port; or DTMF clock output 4 bits of Port 0: 8-bit quasi-bidirectional I/O port crystal oscillator/external clock input crystal oscillator output 4 bits of Port 0: 8-bit quasi-bidirectional I/O port 3 bits of Port 1: 8-bit quasi-bidirectional I/O port ground DTMF output positive supply voltage 4 bits of Port 1: 8-bit quasi-bidirectional I/O port 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output 1 bit of Port 2: 4-bit quasi-bidirectional I/O port
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Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
6 FREQUENCY GENERATOR
PCD3350A
A versatile frequency generator section with built-in programmable clock divider is provided (see Fig.3). The clock divider allows the DTMF section to run either with the main clock frequency (fDTMF = fxtal) or with a third of it (fDTMF = 13 x fxtal) depending on the state of the divider control bit DIV3 (see Table 4). The frequency generator includes precision circuitry for dual tone multifrequency (DTMF) signals, which is typically used for tone dialling telephone sets. 6.1 6.1.1 Frequency generator derivative registers HIGH AND LOW GROUP FREQUENCY REGISTERS
The TONE output can alternatively issue twelve modem frequencies for data rates between 300 and 1200 bits/s. In addition to DTMF and modem frequencies, two octaves of musical scale in steps of semitones are available. Their frequencies are provided either in purely sinusoidal form on the TONE output or as a square wave on the port line P1.7/MDY. The latter is typically for ringer applications in telephone sets. If no frequency output is selected the TONE output is in 3-state mode.
Table 2 gives the addresses, symbols and access types of the High Group Frequency (HGF) and Low Group Frequency (LGF) registers, used to set the frequency output. Table 2 Hexadecimal addresses, symbols, access types and bit symbols of the frequency registers REGISTER SYMBOL HGF LGF ACCESS TYPE W W BIT SYMBOLS 7 H7 L7 6 H6 L6 5 H5 L5 4 H4 L4 3 H3 L3 2 H2 L2 1 H1 L1 0 H0 L0
REGISTER ADDRESS 11H 12H 6.1.2 Table 3 7 0 Table 4 BIT 7 to 3 2
CLOCK AND MELODY CONTROL REGISTER (MDYCON) Clock and Melody Control Register, MDYCON (address 13H; access type R/W) 6 0 5 0 4 0 3 0 2 EDCO 1 DIV3 0 EMO
Description of MDYCON bits SYMBOL - EDCO These bits are set to a logic 0. Enable DTMF clock output. If bit EDCO = 0, then DP1.7/DCO is a general purpose derivative port line. If bit EDCO = 1, then DP1.7/DCO is the DTMF clock output. EDCO = 1 does not inhibit the port instructions for DP1.7/DCO. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of DP1.7/DCO must remain set to avoid conflicts between DTMF clock and port outputs. Enable DTMF clock divider. If bit DIV3 = 0, then the DTMF clock fDTMF = fxtal. If bit DIV3 = 1, then fDTMF = 13 x fxtal. Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line. If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by port instructions. However, the port flip-flop of P1.7/MDY must remain set to avoid conflicts between melody and port outputs. When the HGF contents are zero while EMO = 1, P1.7/MDY is in the HIGH state. DESCRIPTION
1 0
DIV3 EMO
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Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
PCD3350A
handbook, full pagewidth
fxtal
CLOCK DIVIDER
fDTMF
PORT/CLOCK OUTPUT LOGIC
DP1.7/ DCO
8
CLOCK AND MELODY CONTROL REGISTER square wave
PORT/MELODY OUTPUT LOGIC
P1.7/ MDY
8 HGF REGISTER
DIGITAL SINE WAVE SYNTHESIZER DAC SWITCHED CAPACITOR BANDGAP VOLTAGE REFERENCE DAC SWITCHED CAPACITOR LOW-PASS FILTER
8 INTERNAL BUS
RC LOW-PASS FILTER
MGB782
TONE
8 LGF REGISTER
DIGITAL SINE WAVE SYNTHESIZER
Fig.3
Block diagram of the frequency generator, melody output (P1.7/MDY) and DTMF clock output (DP1.7/DCO).
6.2
Melody output (P1.7/MDY)
6.3
DTMF clock divider and output (DP1.7/DCO)
The melody output (P1.7/MDY) is very useful for generating musical notes when a purely sinusoidal signal is not required, such as for ringer applications. The square wave (duty cycle = 1223 or 52%) will include the attenuated harmonics of the base frequency, which is defined by the contents of the HGF register (Table 2). However, even higher frequency notes may be produced since the low-pass filtering on the TONE output is not applied to the P1.7/MDY output. This results in the minimum decimal value x in the HGF register (see equation in Section 6.4) being 2 for the P1.7/MDY output, rather than 60 for the TONE output. A sinusoidal TONE output is produced at the same time as the melody square wave, but due to the filtering, the higher frequency sine waves produced when x < 60 will not appear at the TONE output. Since the melody output is shared with P1.7, the port flip-flop of P1.7 has to be set HIGH before using the melody output. This is to avoid conflicts between melody and port outputs. The melody output drive depends on the configuration of port P1.7/MDY, see Chapter 14, Table 27.
The DTMF clock divider allows the DTMF part to run either with the main clock frequency (fDTMF = fxtal) or with a third of it (fDTMF = 13 x fxtal) depending on the state of the divider control bit DIV3 in register MDYCON. For low power applications, a 3.58 MHz quartz crystal or PXE resonator can be chosen together with the divide-by-one function of the clock divider. For other applications a 10.74 MHz quartz crystal or PXE resonator may be chosen together with the divide-by-three function of the clock divider. This triples the program speed of the microcontroller, thereby keeping the assumed DTMF frequency of 3.58 MHz. Since a 3.58 MHz clock is needed for peripheral telephony circuits such as the analog voice scrambler/descrambler PCD4440T, a switchable DTMF clock output is provided depending on the state of the enable clock output bit EDCO in register MDYCON.
1996 Dec 18
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
If EDCO = 1 and DIV3 = 1 in the MDYCON register: a square wave with the frequency fDTMF = 13 x fxtal is output on the derivative port line DP1.7/DCO. If EDCO = 1 and DIV3 = 0: a square wave with the frequency fDTMF = fxtal is output on the derivative port line DP1.7/DCO. The melody output drive depends on the configuration of port P1.7/MDY, see Chapter 14, Table 27. 6.4 Frequency registers
PCD3350A
The relationships between telephone keyboard symbols, DTMF frequency pairs and the frequency register contents are given in Table 6. Table 5 DTMF standard frequencies and their implementation; value = LGF, HGF contents FREQUENCY (Hz) STANDARD 697 770 852 941 1209 1336 1477 1633 GENERATED 697.90 770.46 850.45 943.23 1206.45 1341.66 1482.21 1638.24 DEVIATION (%) 0.13 0.06 -0.18 0.24 -0.21 0.42 0.35 0.32 (Hz) 0.90 0.46 -1.55 2.23 -2.55 5.66 5.21 5.24
VALUE (HEX) DD C8 B5 A3 7F 72 67 5D Table 6
The two frequency registers HGF and LGF define two frequencies. From these, the digital sine synthesizers together with the Digital-to-Analog Converters (DACs) construct two sine waves. Their amplitudes are precisely scaled according to the bandgap voltage reference. This ensures tone output levels independent of supply voltage and temperature. The amplitude of the Low Group Frequency sine wave is attenuated by 2 dB compared to the amplitude of the High Group Frequency sine wave. The two sine waves are summed and then filtered by an on-chip switched capacitor and RC low-pass filters. These guarantee that all DTMF tones generated fulfil the CEPT recommendations with respect to amplitude, frequency deviation, total harmonic distortion and suppression of unwanted frequency components. The value 00H in a frequency register stops the corresponding digital sine synthesizer. If both frequency registers contain 00H, the whole frequency generator is shut off, resulting in lower power consumption. The frequency `f' of the sine wave generated from either of the frequency registers is a function of the clock frequency `fxtal' and the decimal value `x' held in the register. The equation relating these variables is: f xtal f = -------------------------------- ; where 60 x 255. [ 23 ( x + 2 ) ] The frequency limitation given by x 60 is due to the low-pass filters which would attenuate higher frequency sine waves. 6.5 DTMF frequencies
Dialling symbols, corresponding DTMF frequency pairs and frequency register contents LGF VALUE (HEX) A3 DD DD DD C8 C8 C8 B5 B5 B5 DD C8 B5 A3 A3 A3 HGF VALUE (HEX) 72 7F 72 67 7F 72 67 7F 72 67 5D 5D 5D 5D 7F 67
TELEPHONE DTMF FREQ. KEYBOARD PAIRS SYMBOLS (Hz) 0 1 2 3 4 5 6 7 8 9 A B C D * # (941, 1336) (697, 1209) (697, 1336) (697, 1477) (770, 1209) (770, 1336) (770, 1477) (852, 1209) (852, 1336) (852, 1477) (697, 1633) (770, 1633) (852, 1633) (941, 1633) (941, 1209) (941, 1477)
Assuming an oscillator frequency fxtal = 3.58 MHz, the DTMF standard frequencies can be implemented as shown in Table 5.
1996 Dec 18
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
6.6 Modem frequencies Table 8
PCD3350A
Musical scale frequencies and their implementation HGF VALUE (HEX) F8 EA DD D0 C5 B9 AF A5 9C 93 8A 82 7B 74 6D 67 61 5C 56 51 4D 48 44 40 3D FREQUENCY (Hz) STANDARD(1) 622.3 659.3 698.5 740.0 784.0 830.6 880.0 923.3 987.8 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.7 1975.5 2093.0 2217.5 2349.3 2489.0 GENERATED 622.5 659.5 697.9 741.1 782.1 832.3 879.3 931.9 985.0 1044.5 1111.7 1179.0 1245.1 1318.9 1402.1 1482.2 1572.0 1655.7 1768.5 1875.1 1970.0 2103.3 2223.3 2358.1 2470.4
Again assuming an oscillator frequency fxtal = 3.58 MHz, the standard modem frequencies can be implemented as in Table 7. It is suggested to define the frequency by the HGF register while the LGF register contains 00H, disabling Low Group Frequency generation. Table 7 HGF VALUE (HEX) 9D 82 8F 79 80 45 76 48 5C 52 4B 44 Notes 1. Standard is V.21. 2. Standard is Bell 103. 3. Standard is Bell 202. 4. Standard is V.23. 6.7 Musical scale frequencies Standard modem frequencies and their implementation FREQUENCY (Hz) MODEM 980(1) 1180(1) 1070(2) 1270(2) 1200(3) 2200(3) 1300(4) 2100(4) 1650(1) 1850(1) 2025(2) 2225(2) GENERATED 978.82 1179.03 1073.33 1265.30 1197.17 2192.01 1296.94 2103.14 1655.66 1852.77 2021.20 2223.32 DEVIATION (%) -0.12 -0.08 0.31 -0.37 -0.24 -0.36 -0.24 0.15 0.34 0.15 -0.19 -0.08 (Hz) -1.18 -0.97 3.33 -4.70 -2.83 -7.99 -3.06 3.14 5.66 2.77 -3.80 -1.68
NOTE D#5 E5 F5 F#5 G5 G#5 A5 A#5 B5 C6 C#6 D6 D#6 E6 F6 F#6 G6 G#6 A6 A#6 B6 C7 C#7 D7 D#7 Note
Finally, two octaves of musical scale in steps of semitones can be realized, again assuming an oscillator frequency fxtal = 3.58 MHz (Table 8). It is suggested to define the frequency by the HGF register while the LGF contains 00H, disabling Low Group Frequency generation.
1. Standard scale based on A4 @ 440 Hz.
1996 Dec 18
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
7 EEPROM AND TIMER 2 ORGANIZATION
PCD3350A
The PCD3350A has 256 bytes of Electrically Erasable Programmable Read Only Memory (EEPROM). Such non-volatile storage provides data retention without the need for battery backup. In telecom applications, the EEPROM is used for storing redial numbers and for short dialling of frequently used numbers. More generally, EEPROM may be used for customizing microcontrollers, such as to include a PIN code or a country code, to define trimming parameters, to select application features from the range stored in ROM. The most significant difference between a RAM and an EEPROM is that a bit in EEPROM, once written to a logic 1, cannot be cleared by a subsequent write operation. Successive write accesses actually perform a logical OR with the previously stored information. Therefore, to clear a bit, the whole byte must be erased and re-written with the particular bit cleared. Thus, an erase-and-write operation is the EEPROM equivalent of a RAM write operation.
Whereas read access times to an EEPROM are comparable to RAM access times, write and erase access times are much slower at 5 ms each. To make these operations more efficient, several provisions are available in the PCD3350A. First, the EEPROM array is structured into 64 four-byte pages (see Fig.4) permitting access to 4 bytes in parallel (write page, erase/write page and erase page). It is also possible to erase and write individual bytes. Finally, the EEPROM address register provides auto-incrementing, allowing very efficient read and write accesses to sequential bytes. To simplify the erase and write timing, the derivative 8-bit down-counter (Timer 2) with reload register is provided. In addition to EEPROM timing, Timer 2 can be used for general real-time tasks, such as for measuring signal duration and for defining pulse widths.
1996 Dec 18
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
PCD3350A
handbook, full pagewidth
6 8 EEPROM ADDRESS REGISTER
2 2 : 4 DECODER EEPROM LATCH 0 EEPROM LATCH 1 EEPROM LATCH 2 EEPROM LATCH 3 F0 F1 F2 F3 256-byte EEPROM ARRAY (64 4-byte PAGES) 6 : 64 DECODER
8
8 8 EEPROM TEST REGISTER
8 EEPROM CONTROL REGISTER
8 TIMER 2 RELOAD REGISTER 8 8 TIMER 2 REGISTER (T2) 8 INTERNAL BUS
1 f 480 xtal
MGB783
T2F set on underflow
Fig.4 Block diagram of the EEPROM and Timer 2.
1996 Dec 18
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
7.1 7.1.1 EEPROM registers EEPROM CONTROL REGISTER (EPCR)
PCD3350A
The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register, as detailed in Tables 9, 10 and 11. Table 9 7 STT2 EEPROM Control Register, EPCR (address 04H, access type R/W) 6 ET2I 5 T2F 4 EWP 3 MC3 2 MC2 1 MC1 0 0
Table 10 Description of EPCR bits BIT 7 6 5 4 3 2 1 0 SYMBOL STT2 ET2I T2F EWP MC3 MC2 MC1 - This bit is set to a logic 0. DESCRIPTION Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2 decrements from reload value. Enable T2 interrupt. If ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1, then T2F event can request interrupt. Timer 2 flag. Set when T2 underflows (or by program); reset by program. Erase or write in progress (EWP). Set by program (EWP starts EEPROM erase and/or write and Timer 2). Reset at the end of EEPROM erase and/or write. Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as shown in Table 11.
Table 11 Mode selection; X = don't care EWP 0 0 1 1 1 X X X MC3 0 0 0 1 1 0 1 1 MC2 0 1 1 0 1 0 0 1 MC1 0 0 X 0 1 1 1 0 read byte increment mode write page erase/write page erase page not allowed DESCRIPTION
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
7.1.2 EEPROM ADDRESS REGISTER (ADDR)
PCD3350A
The EEPROM Address Register (ADDR) determines the EEPROM location to which an EEPROM access is directed. As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero. See Tables 12 and 13. Table 12 EEPROM Address Register, ADDR (address 01H, access type R/W) 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0
Table 13 Description of ADDR bits BIT 7 to 2 1 to 0 SYMBOL AD7 to AD2 AD1 to AD0 DESCRIPTION AD7 to AD2 select one of 64 pages. AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0 and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment mode (see Table 11) is active during page setup, the subcounter consisting of AD0 and AD1 increments after every write to an EEPROM latch, thus enhancing access to sequential EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when AD0 and AD1 are both a logic 1.
7.1.3
EEPROM DATA REGISTER (DATR)
Table 14 EEPROM Data Register, DATR (address 03H; access type R/W) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 15 Description of DATR bits BIT 7 to 0 SYMBOL D7 to D0 DESCRIPTION The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write operation to DATR, loads data into the EEPROM latch (see Fig.4) defined by bits AD0 and AD1 of ADDR.
7.1.4
EEPROM TEST REGISTER (TST)
The EEPROM Test Register is used for testing purposes during device manufacture. It must not be accessed by the device user.
1996 Dec 18
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Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
7.2 EEPROM latches
PCD3350A
The four EEPROM latches (EEPROM Latch 0 to 3; Fig.4) cannot be read by user software. Due to their construction, the latches can only be preset, but not cleared. Successive write operations through DATR to the EEPROM latches actually perform a logical OR with the previously stored data in EEPROM. The EEPROM latches are reset at the conclusion of any EEPROM cycle. 7.3 EEPROM flags
page, are irrelevant during write and erase cycles. However, write and erase cycles need not affect all bytes of the page. The EEPROM flags F0 to F3 (see Fig.4) determine which bytes within the EEPROM page are affected by the erase and/or write cycles. A byte whose corresponding EEPROM flag is zero remains unchanged. With erase page, a byte is erased if its corresponding EEPROM flag is set. With write page, data in EEPROM Latch 0 to 3 (Fig.4) are ORed to the individual page bytes if and only if the corresponding EEPROM flags are set. In an erase/write cycle, F0 to F3 select which page bytes are erased and ORed with the corresponding EEPROM latches. ORing, in this case, means that the EEPROM latches are copied to the selected page bytes. The described page-wise organization of erase and write cycles allows up to four bytes to be individually erased or written within 5 ms. This advantage necessitates a preparation step, called page setup, before the actual erase and/or write cycle can be executed. Page setup controls EEPROM latches and EEPROM flags. This will be described in the Sections 7.5.1 to 7.5.5. 7.5.1 PAGE SETUP
The four EEPROM flags (F0 to F3; Fig.4) cannot be directly accessed by user software. An EEPROM flag is set as a side-effect when the corresponding EEPROM latch is written through DATR. The EEPROM flags are reset at the conclusion of any EEPROM cycle. 7.4 EEPROM macros
The instruction sequence used in an EEPROM access should be treated as an indivisible entity. Erroneous programs result if ADDR, DATR, RELR or EPCR are inadvertently changed during an EEPROM cycle or its setup. Special care should be taken if the program may asynchronously divert due to an interrupt. A new access to the EEPROM may only be initiated when no write, erase or erase/write cycles are in progress. This can be verified by reading bit EWP (register EPCR). For write, erase and erase/write cycles, it is assumed that the Timer 2 Reload Register (RELR) has been loaded with the appropriate value for a 5 ms delay, which depends on fxtal (see Table 22). The end of a write, erase or erase/write cycle will be signalled by a cleared EWP and by a Timer 2 interrupt provided that ET2I = 1 and that the derivative interrupt is enabled. 7.5 EEPROM access
Page setup is a preparation step required before write page, erase page and erase/write page cycles. As previously described, these page operations include single-byte write, erase and erase/write as a special case. EEPROM flags F0 to F3 determine which page bytes will be affected by the mentioned page operations. EEPROM Latch 0 to 3 must be preset through DATR to specify the write cycle data to EEPROM and to set the EEPROM flags as a side-effect. Obviously, the actual preset value of the EEPROM latches is irrelevant for erase page. Preset of one, two, three or all four EEPROM latches and the corresponding EEPROM flags can be performed by repeatedly defining ADDR and writing to DATR (see Table 16). If more than one EEPROM latch must be preset, the subcounter consisting of AD0 and AD1 can be induced to auto-increment after every write to DATR, thus stepping through all EEPROM latches. For this purpose, increment mode (Table 11) must be selected. Auto-incrementing stops at EEPROM Latch 3. It is not mandatory to start at EEPROM Latch 0 as in shown in Table 17. Note that AD2 to AD7 are irrelevant during page setup. They will usually specify the intended EEPROM page, anticipating the subsequent page cycle.
One read, one write, one erase/write and one erase access are defined by bits EWP and MC1 to MC3 in the EPCR register; see Table 9. Read byte retrieves the EEPROM byte addressed by ADDR when DATR is read. Read cycles are instantaneous. Write and erase cycles take 5 ms, however. Erase/write is a combination of an erase and a subsequent write cycle, consequently taking 10 ms. As their names imply, write page, erase page and erase/write page are applied to a whole EEPROM page. Therefore, bits AD0 and AD1 of register ADDR (see Table 12), defining the byte location within an EEPROM
1996 Dec 18
15
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
From now on, it will be assumed that AD2 to AD7 will contain the intended EEPROM page address after page setup. Table 16 Page setup; preset INSTRUCTION MOV A, #addr MOV ADDR, A MOV A, #data MOV DATR, A RESULT address of EEPROM latch send address to ADDR load write, erase/write or erase data send data to addressed EEPROM latch 7.5.3 WRITE PAGE
PCD3350A
The write cycle performs a logical OR between the data in the EEPROM latches and that in the addressed EEPROM page. To actually copy the data from the EEPROM latches, the corresponding bytes in the page should previously have been erased. The EEPROM latches are preset as described in Section 7.5.1. The actual transfer to the EEPROM is then performed as shown in Table 19. The last instruction also starts Timer 2. The data in the EEPROM latches are ORed with that in the corresponding page bytes within 5 ms. A single-byte write is simply a special case of `write page'. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by bits AD2 to AD7) and to EEPROM Latch 0 (by bits AD0 and AD1). This allows efficient coding of multi-page write operations. Table 19 Write page INSTRUCTION MOV A, #EWP + MC2 MOV EPCR, A 7.5.4 RESULT `write page' control word start `write page' cycle
Table 17 Page setup; auto-incrementing INSTRUCTION MOV A, #MC2 MOV EPCR, A MOV A, #baddr MOV ADDR, A MOV A, R0 MOV DATR, A MOV A, R1 MOV DATR, A MOV A, R2 MOV DATR, A MOV A, R3 MOV DATR, A 7.5.2 READ BYTE RESULT increment mode control word select increment mode EEPROM Latch 0 address (AD0 = AD1 = 0) send EEPROM Latch 0 address to ADDR load 1st byte from Register 0 send 1st byte to EEPROM Latch 0 load 2nd byte from Register 1 send 2nd byte to EEPROM Latch 1 load 3rd byte from Register 2 send 3rd byte to EEPROM Latch 2 load 4th byte from Register 3 send 4th byte to EEPROM Latch 3
ERASE/WRITE PAGE
The EEPROM latches are preset as described in Section 7.5.1. The page bytes corresponding to the asserted flags (among F0 to F3) are erased and re-written with the contents of the respective EEPROM latches. The last instruction also starts Timer 2. Erasure takes 5 ms upon which Timer Register T2 reloads for another 5 ms cycle for writing. The top cycles together take 10 ms. A single-byte erase/write is simply a special case of `erase/write page'. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by AD2 to AD7) and to EEPROM Latch 0 (by AD0 and AD1). This allows efficient coding of multi-page erase/write operations. Table 20 Erase/write page INSTRUCTION MOV A, #EWP + MC3 MOV EPCR, A RESULT `erase/write page' control word start `erase/write page' cycle
Since ADDR auto-increments after a read cycle regardless of the page boundary, successive bytes can efficiently be read by repeating the last instruction. Table 18 Read byte INSTRUCTION MOV A, #RDADDR MOV ADDR, A MOV A, DATR RESULT load read address send address to ADDR read EEPROM data
1996 Dec 18
16
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
7.5.5 ERASE PAGE
PCD3350A
The EEPROM flags are set as described in Section 7.5.1. The corresponding page bytes are erased. The last instruction also starts Timer 2. Erasure takes 5 ms. A single-byte erase is simply a special case of `erase page'. Note that ADDR does not auto-increment after an erase cycle. Table 21 Erase page INSTRUCTION MOV A, #EWP + MC3 + MC2 + MC1 MOV EPCR, A RESULT `erase page' control word start `erase page' cycle
The second underflow of an erase/write cycle and the first underflow of write page and erase page conclude the corresponding EEPROM cycle. Timer 2 is stopped, T2F is set whereas EWP and MC1 to MC3 are cleared. Table 22 Reload values as a function of fxtal fxtal (MHz) 1 2 3.58 6 10.74 16 Note 1. The reload value is (5 x 10-3 x 1480 x fxtal) - 1; fxtal in MHz. 7.6.2 TIMER 2 AS A GENERAL PURPOSE TIMER RELOAD VALUE(1) (HEX) 0A 14 25 3E 6F A6
7.6
Timer 2
Timer 2 is a 8-bit down-counter decremented at a rate of 1 480 x fxtal. It may be used either for EEPROM timing or as a general purpose timer. Conflicts between the two applications should be carefully avoided. 7.6.1 TIMER 2 FOR EEPROM TIMING
When used for EEPROM timing, Timer 2 serves to generate the 5 ms intervals needed for erasing or writing the EEPROM. At the decrement rate of 1480 x fxtal, the reload value for a 5 ms interval is a function of fxtal. Table 22 summarizes the required reload values for a number of oscillator frequencies. Timer 2 is started by setting bit EWP in the EPCR. The Timer Register T2 is loaded with the reload value from RELR. T2 decrements to zero. For an erase/write cycle, underflow of T2 indicates the end of the erase operation. Therefore, Timer Register T2 is reloaded from RELR for another 5 ms interval during which the flagged EEPROM latches are copied to the corresponding bytes in the page addressed by ADDR.
When used for purposes other than EEPROM timing, Timer 2 is started by setting STT2. The Timer 2 Register T2 (see Table 28) is loaded with the reload value from RELR. T2 decrements to zero. On underflow, T2 is reloaded from RELR, T2F is set and T2 continues to decrement. Timer 2 can be stopped at any time by clearing STT2. The value of T2 is then held and can be read out. After setting STT2 again, Timer 2 decrements from the reload value. Alternatively, it is possible to read T2 `on the fly' i.e. while Timer 2 is operating.
1996 Dec 18
17
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
8 REAL-TIME CLOCK
PCD3350A
The Real Time Clock (RTC) consists of a 32 kHz crystal oscillator, a 32 kHz to 1 second or 1 minute divider chain, an 8-bit Frequency Adjustment Register and the Clock Control Register. The complete RTC section works independently of the microcontroller status, even in Idle and Stop mode. 8.1 Oscillator
Since the clock interrupt is used to let the microcontroller leave the Stop mode, it is ORed to the external interrupt (CE/T0) and has the same functionality, e.g. it must be enabled in the Clock Control Register (bit ECI) and by execution of the instruction `EN I'. The clock interrupt will then be treated as an external interrupt. Additionally, the divider chain generates a 16 kHz clock (RCO) that can be routed through derivative port line DP0.0/RCO, controlled by bit ERCO in the Clock Control Register. 8.3 Frequency adjustment
The internal 32 kHz oscillator needs an external quartz crystal with a frequency of 32768.00 Hz (a positive deviation up to +259 x 10-6 is allowed) and an external feedback resistor between pins RTC1 and RTC2; 4.7 M is recommended. It is controlled by the RUN-bit in the Clock Control Register. 8.2 Divider chain
The frequency adjustment is used to extend the interrupt time by defining the number of 16 kHz clocks in the Frequency Adjustment Register that will be counted twice within the first second period after a minute interrupt. If the second interrupt is used (ITS = 1), every 60th interval may be up to 15.3 ms longer than the others as a result of the frequency adjustment. The adjusted Minute Interrupt Time (MIT) now shows a maximum deviation of 0.5 x 10-6.
The divider chain operates with the 32 kHz oscillator output and divides this signal down to two clocks with a period of 1 second or 1 minute. Depending on bit ITS in the Clock Control Register, the falling edge of the seconds or minutes clock is used to set the Clock Interrupt Flag (CIF) in the Clock Control Register.
1996 Dec 18
18
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
8.4 8.4.1 Real-time clock derivative registers CLOCK CONTROL REGISTER (CLCR)
PCD3350A
The register access type is R/W and the value at reset is 00H. Table 23 Clock Control Register, CLCR (address 20H) 7 0 6 TST2 5 TST1 4 ERCO 3 RUN 2 ITS 1 CIF 0 ECI
Table 24 Description of CLCR bits BIT 7 6 5 4 SYMBOL - TST2 TST1 ERCO This bit is set to a logic 0. Test 2 input. This is a testing bit; has to be fixed at a logic 0 by user software. Test 1 input. This is a testing bit; has to be fixed at a logic 0 by user software. Enable 16 kHz clock output. If ERCO = 0, then the DP0.0/RCO is a derivative port line. If ERCO = 1, then DP0.0./RCO is a 16 kHz clock output. ERCO = 1 does not inhibit the port instructions for DP0.0/RCO. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of DP0.0/RCO must remain set to avoid conflicts between 16 kHz clock and port outputs. Clock run or stop bit. If RUN = 0, then the oscillator is stopped and the clock is reset. If RUN = 1, then the oscillator and the clock are running. Interrupt Time Select. If ITS = 1, then the interrupt time is one second. If ITS = 0, then the interrupt time is one minute. Clock Interrupt Flag. Set by hardware, if RTC divider chain overflows (every second or minute depending on ITS) or by program. Reset by program. Enable Clock Interrupt. If ECI = 0, then CIF event cannot request interrupt. If ECI = 1, then CIF event requests interrupt. DESCRIPTION
3 2 1 0
RUN ITS CIF ECI
8.4.2
FREQUENCY ADJUSTMENT REGISTER (FAR)
The frequency adjustment value of the RTC is defined by the 8-bit Frequency Adjustment Register. The register access type is R/W. The value of FAR at reset is 00H. The significance of the individual bits of FAR can be illustrated by the following equation: 14 ----------- f RCO FAR Minute Interrupt Time (MIT) = 60 x 2 + ----------14 2 where fRCO = RTC frequency and `FAR' is the decimal contents of the Frequency Adjustment Register. Table 26 shows the recommended correction factor FAR for all allowed RTC frequencies fRCO. Table 25 Frequency Adjustment Register, FAR (address 21H) 7 FAR7 6 FAR6 5 FAR5 4 FAR4 3 FAR3 2 FAR2 1 FAR1 0 FAR0
1996 Dec 18
19
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
Table 26 FAR as a result of fRCO fRCO 16384.000 16384.018 16384.033 16384.051 16384.066 16384.084 16384.100 16384.117 16384.135 16384.150 16384.168 16384.184 16384.201 16384.217 16384.234 16384.250 16384.268 16384.283 16384.301 16384.316 16384.334 16384.350 16384.367 16384.385 16384.400 16384.418 16384.434 16384.451 16384.467 16384.484 FAR (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D fRCO 16384.500 16384.518 16384.533 16384.551 16384.566 16384.584 16384.600 16384.617 16384.635 16384.650 16384.668 16384.684 16384.701 16384.717 16384.734 16384.750 16384.768 16384.783 16384.801 16384.816 16384.834 16384.850 16384.867 16384.885 16384.900 16384.918 16384.934 16384.951 16384.967 16384.984 16385.000 FAR (HEX) 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C fRCO 16385.018 16385.033 16385.051 16385.066 16385.084 16385.100 16385.117 16385.135 16385.150 16385.168 16385.184 16385.201 16385.217 16385.234 16385.250 16385.268 16385.283 16385.301 16385.316 16385.334 16385.350 16385.367 16385.385 16385.400 16385.418 16385.434 16385.451 16385.467 16385.484 16385.500 16385.518
PCD3350A
FAR (HEX) 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B
1996 Dec 18
20
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
fRCO 16385.533 16385.551 16385.566 16385.584 16385.600 16385.617 16385.635 16385.650 16385.668 16385.684 16385.701 16385.717 16385.734 16385.750 16385.768 16385.783 16385.801 16385.816 16385.834 16385.850 16385.867 16385.885 16385.900 16385.918 16385.934 16385.951 16385.967 16385.984 FAR (HEX) 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 fRCO 16386.000 16386.018 16386.033 16386.051 16386.066 16386.084 16386.100 16386.117 16386.135 16386.150 16386.168 16386.184 16386.201 16386.217 16386.234 16386.250 16386.268 16386.283 16386.301 16386.316 16386.334 16386.350 16386.367 16386.385 16386.400 16386.418 16386.434 16386.451 FAR (HEX) 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 fRCO 16386.467 16386.484 16386.500 16386.518 16386.533 16386.551 16386.566 16386.584 16386.600 16386.617 16386.635 16386.650 16386.668 16386.684 16386.701 16386.717 16386.734 16386.750 16386.768 16386.783 16386.801 16386.816 16386.834 16386.850 16386.867 16386.885 16386.900 16386.918
PCD3350A
FAR (HEX) 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
1996 Dec 18
21
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
fRCO 16386.934 16386.951 16386.967 16386.984 16387.000 16387.018 16387.033 16387.051 16387.066 16387.084 16387.100 16387.117 16387.135 16387.150 16387.168 16387.184 16387.201 16387.217 16387.234 16387.250 16387.268 16387.283 16387.301 16387.316 16387.334 16387.350 16387.367 FAR (HEX) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA fRCO 16387.385 16387.400 16387.418 16387.434 16387.451 16387.467 16387.484 16387.500 16387.518 16387.533 16387.551 16387.566 16387.584 16387.600 16387.617 16387.635 16387.650 16387.668 16387.684 16387.701 16387.717 16387.734 16387.750 16387.768 16387.783 16387.801 16387.816 FAR (HEX) CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 fRCO 16387.834 16387.850 16387.867 16387.885 16387.900 16387.918 16387.934 16387.951 16387.967 16387.984 16388.002 16388.018 16388.035 16388.051 16388.068 16388.084 16388.102 16388.117 16388.135 16388.152 16388.168 16388.186 16388.201 16388.219 16388.234 16384.000
PCD3350A
FAR (HEX) E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
1996 Dec 18
22
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
9 DERIVATIVE INTERRUPTS 12 IDLE MODE
PCD3350A
One derivative interrupt event is defined. It is controlled by bits T2F and ET2I in the EPCR (see Tables 9 and 10). The derivative interrupt event occurs when T2F is set. This request is honoured under the following circumstances: * No interrupt routine proceeds * No external interrupt request is pending * The derivative interrupt is enabled * ET2I is set. The derivative interrupt routine must include instructions that will remove the cause of the derivative interrupt by explicitly clearing T2F. If the derivative interrupt is not used, T2F may directly be tested by the program. Obviously, T2F can also be asserted under program control, e.g. to generate a software interrupt. Although the clock interrupt is part of a derivative function it is linked to the external interrupt. A clock interrupt request is honoured under the following circumstances: * No interrupt routine proceeds * No external interrupt request is pending * The enable clock interrupt bit in the derivative clock control register is set. 10 TIMING Although the PCD3350A operates over a clock frequency range from 1 to 16 MHz, fxtal = 3.58 MHz or 10.74 MHz will usually be chosen to take full advantage of the frequency generator (DTMF) section. 11 RESET In addition to the conditions given in the "PCD33xxA Family" data sheet, all derivative registers are cleared in the reset state.
In Idle mode all derivative functions remain operative, i.e.: * DTMF generator * DTMF clock divider and output * 32 kHz crystal oscillator and RTC * EEPROM and Timer 2 sections. 13 STOP MODE Since the oscillator is switched off, the frequency generator, the EEPROM and the Timer 2 sections receive no clock. It is suggested to clear both the HGF and the LGF registers before entering Stop mode. This will cut off the biasing of the internal amplifiers, considerably reducing current requirements. The Stop mode must not be entered while an erase and/or write access to EEPROM is in progress. The STOP instruction may only be executed when EWP in EPCR is zero. The Timer 2 section is frozen during Stop mode. After exit from Stop mode by a HIGH level on CE/T0, Timer 2 proceeds from the held state. The 32 kHz crystal oscillator and the RTC section remain operative during Stop mode (depending only on bit RUN in the Clock Control Register). In addition to the description in the "PCD33xxA Family" data sheet, Stop mode may be left by a clock interrupt event (see Chapter 9).
1996 Dec 18
23
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
14 SUMMARY OF I/O PORTS AND ROM MASK OPTIONS All standard quasi-bidirectional I/O ports are available; see "PCD33xxA Family" data sheet. * Port 0: 8 parallel port lines P0.0 to P0.7 * Port 1: 8 parallel port lines P1.0 to P1.7 * Port 2: 4 parallel port lines P2.0 to P2.3. In addition to the standard ports, two derivative I/O ports are available: * Derivative Port 0: 6 parallel port lines DP0.0 to DP0.5 (register DP0L) * Derivative Port 1: 8 parallel port lines DP1.0 to DP1.7 (register DP1L).
PCD3350A
The port options and the other ROM mask options are listed in Table 27. See Table 28 for the addresses of DP0L and DP1L. Table 27 ROM mask options FUNCTION IMPLEMENTED IN ROM Program/data Port Output P0.0 to P0.7 P1.0 to P1.6 P1.7/MDY; note 1 P2.0 to P2.3 DP0.0 to DP0.5 DP1.0 to DP1.6 DP1.7/DCO; note 2 Port State after reset P0.0 to P0.7 P1.0 to P1.6 P1.7/MDY P2.0 to P2.3 DP0.0 to DP0.5 DP1.0 to DP1.6 DP1.7/DCO Oscillator Transconductance Power-on-reset Power-on-reset voltage level: VPOR Notes 1. If standard (Option 1) or push-pull (Option 3) output is chosen, the P1.7/MDY output becomes a push-pull output. If open-drain (Option 2) is chosen, the P1.7/MDY output becomes an open-drain output. 2. If standard (Option 1) or push-pull (Option 3) output is chosen, the DP1.7/DCO output becomes a push-pull output. If open-drain (Option 2) is chosen, the DP1.7/DCO output becomes an open-drain output. 1.2 to 3.6 V in increments of 100 mV; OFF LOW (gmL) MEDIUM (gmM) HIGH (gmH) set set set set set set set reset reset reset reset reset reset reset - - - - - - - standard standard standard standard standard standard standard open-drain open-drain open-drain open-drain open-drain open-drain open-drain push-pull push-pull push-pull push-pull push-pull push-pull push-pull OPTION Any mix of instructions and data up to ROM size of 8 kbytes.
1996 Dec 18
24
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
15 SUMMARY OF DERIVATIVE REGISTERS Table 28 Register map ADDR. (HEX) 00 01 02 03 04 05 06 07 not used EEPROM Address Register (ADDR) not used EEPROM Data Register (DATR) EEPROM Control Register (EPCR) Timer 2 Reload Register (RELR) Timer 2 Register (T2) Test Register (TST) High Group Frequency Register (HGF) Low Group Frequency Register (LGF) Clock and Melody Control Register (MDYCON) Clock Control Register (CLCR) Frequency Adjustment Register (FAR) Derivative Port 0 lines (DP0L) Derivative Port 1 lines (DP1L) Derivative Port 0 flip-flop (DP0FF) Derivative Port 1 flip-flop (DP1FF) D7 STT2 R7 T2.7 D6 ET21 R6 T2.6 D5 TF2 R5 T2.5 D4 EWP R4 T2.4 D3 MC3 R3 T2.3 D2 MC2 R2 T2.2 0 AD6 AD5 AD4 AD3 AD2 REGISTER 7 6 5 4 3 2
PCD3350A
1
0
R/W
AD1
AD0
R/W
D1 MC1 R1 T2.1
D0 0 R0 T2.0
R/W R/W R/W R
only for test purposes; not to be accessed by the device user
08 to 10 not used 11 12 13 H7 L7 0 H6 L6 0 H5 L5 0 H4 L4 0 H3 L3 0 H2 L2 DCO H1 L1 DIV3 H0 L0 EMO W W R/W
14 to 1F not used 20 21 0 FAR7 TST2 TST1 ERCO FAR4 RUN ITS CIF ECI FAR0 R/W R/W
FAR6 FAR5
FAR3 FAR2 FAR1
22 to 2F not used 30 31 32 33 0 D1.7 0 F1.7 0 D1.6 0 F1.6 D0.5 D1.5 F0.5 F1.5 D0.4 D1.4 F0.4 F1.4 D0.3 D1.3 F0.3 F1.3 D0.2 D1.2 F0.2 F1.2 D0.1 D1.1 F0.1 F1.1 D0.0 D1.0 F0.0 F1.0 R R R/W R/W
34 to FF not used 16 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices (see "Data Handbook IC14, Section: Handling MOS devices").
1996 Dec 18
25
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
17 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II IO Ptot PO ISS Tstg Tj supply voltage all input voltages DC input current DC output current total power dissipation power dissipation per output ground supply current storage temperature operating junction temperature PARAMETER MIN. -0.5 -0.5 -10 -10 - - -50 -65 -
PCD3350A
MAX. +7.0 VDD + 0.5 +10 +10 125 30 +50 +150 90 V V
UNIT
mA mA mW mW mA C C
18 DC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = -25 to +70 C; all voltages with respect to VSS; fxtal = 3.58 MHz (gmL); fRTC = 32768 to 32768 + (32768 x 200 x 10-6) Hz; unless otherwise specified. SYMBOL Supply VDD supply voltage operating RAM data retention in Stop mode IDD operating supply current see Figs 6 and 7; note 2 VDD = 3 V; value HGF or LGF 0 VDD = 3 V; value HGF = LGF = 0 - - 0.8 0.35 2.7 1.7 3.5 1.6 0.7 6.2 4.2 - mA mA mA mA mA see Fig.5 note 1 1.8 1.0 - - 6 6 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDD = 5 V; fxtal = 10.74 MHz (gmM); - value HGF or LGF 0; DIV3 = 1 VDD = 5 V; fxtal = 10.74 MHz (gmM); - value HGF = LGF = 0 VDD = 5 V; fxtal = 16 MHz (gmH); value HGF = LGF = 0 -
1996 Dec 18
26
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
SYMBOL IDD(idle) PARAMETER supply current (Idle mode) CONDITIONS see Figs 8 and 9; note 2 VDD = 3 V; value HGF or LGF 0 VDD = 3 V; value HGF = LGF =0 - - 0.7 0.25 2.3 1.3 2.4 MIN. TYP.
PCD3350A
MAX. 1.4 0.5 5.5 3.5 -
UNIT mA mA mA mA mA
VDD = 5 V; fxtal = 10.74 MHz (gmM); - value HGF or LGF 0; DIV3 = 1 VDD = 5 V; fxtal = 10.74 MHz (gmM); - value HGF = LGF = 0 VDD = 5 V; fxtal = 16 MHz (gmH); value HGF = LGF = 0 IDD(stp) supply current (Stop mode) see Fig.10; notes 2 and 3 VDD = 1.8 V; Tamb = 25 C; RTC not running - -
1.0 - 2.0
5.5 10 6.0
A A A
VDD = 1.8 V; Tamb = -25 to +70 C; - RTC not running VDD = 1.8 V; Tamb = 25 C; RTC running Inputs VIL VIH ILI IOL IOH IOH1 LOW level input voltage HIGH level input voltage input leakage current VSS VI VDD VDD = 3 V; VO = 0.4 V; see Fig.11 VDD = 3 V; VO = 2.7 V; see Fig.12 VDD = 3 V; VO = 0 V; see Fig.12 VDD = 3 V; VO = 2.6 V; see Fig.13 0 0.7VDD -1 -
- - -
0.3VDD VDD +1 - - -300 -
V V A
Port outputs LOW level output sink current HIGH level pull-up output source current HIGH level push-pull output source current 0.7 -10 - -0.7 3.5 -30 -140 -3.5 mA A A mA
Real-time clock 32 kHz oscillator gm f/f Ci Co VHG(RMS) VLG(RMS) f f VDC Zo Gv THD transconductance frequency adjustment input capacitance (pin 10) output capacitance (pin 11) Vi(p-p) < 50 mV; see Fig.14 2 -0.6 x 10-6 - - 10 - 10 10 50 +0.6 x 10-6 - - pF pF S
TONE output (see Fig.15; notes 1 and 4) HGF voltage (RMS value) LGF voltage (RMS value) frequency deviation DC voltage level output impedance pre-emphasis of group total harmonic distortion Tamb = 25 C; note 5 158 125 -0.6 - - 1.5 - 181 142 - 0.5VDD 100 2.0 -25 205 160 0.6 - 500 2.5 - mV mV % V dB dB
1996 Dec 18
27
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
SYMBOL PARAMETER CONDITIONS MIN. - - TYP.
PCD3350A
MAX. - -
UNIT
EEPROM (notes 1 and 6) ncyc tD(ret) VPOR endurance (erase/write cycles) data retention note 7 105 10 -0.5
years
Power-on-reset Power-on-reset level variation around chosen VPOR LOW transconductance MEDIUM transconductance HIGH transconductance feedback resistor note 8 0 +0.5 V
Oscillator (see Fig. 17) gmL gmM gmH RF Notes 1. TONE output; EEPROM erase and write require VDD 2.5 V: a) TONE output requires fxtal < 4 MHz in case DIV3 = 0. b) TONE output requires fxtal < 12 MHz in case DIV3 = 1. 2. VIL = VSS; VIH = VDD; open-drain outputs connected to VSS; all other outputs open: a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit. b) Typical values: Tamb = 25 C; crystal connected between XTAL1 and XTAL2. 3. VIL = VSS; VIH = VDD; RESET, T1 and CE/T0 at VSS; crystal connected between XTAL1 and XTAL2; open-drain outputs connected to VSS; all other outputs open. 4. Values are specified for DTMF frequencies only (CEPT). 5. Related to the Low Group Frequency (LGF) component (CEPT). 6. After final testing the value of each EEPROM bit is typically logic 1. 7. Verified on sampling basis. 8. VPOR is an option chosen by the user. Depending on its value, it may restrict the supply voltage range. VDD = 5 V VDD = 5 V VDD = 5 V 0.2 0.9 3 0.3 0.4 1.6 4.5 1.0 1.0 3.2 9.0 3.0 mS mS mS M
1996 Dec 18
28
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
PCD3350A
handbook, halfpage f
18 xtal (MHz) 15
MLA493
MGB813
handbook, halfpage
6
IDD (mA) 10.7 MHz HGF LGF = 0 gmM 16 MHz HGF = LGF = 0 gmH -25 oC to 70 oC 2 3.58 MHz HGF LGF gmL 10.7 MHz HGF = LGF = 0 gmM 3.58 MHz HGF = LGF = 0 gmL 1 3 5 VDD (V) 7 0 1 3 5 VDD (V) 7
12
4
9 guaranteed operating range
6
3
0
Measured with crystal between XTAL1 and XTAL2.
Fig.5
Maximum clock frequency (fxtal) as a function of supply voltage (VDD).
Fig.6
Typical operating supply current (IDD) as a function of supply voltage (VDD).
handbook, halfpage
6
MGB828
MGB814
handbook, halfpage
6
IDD (mA) 4 5V
IDD(idle) (mA) 16 MHz HGF = LGF = 0 gmH -25 oC to 70 oC
4
2
2
10.7 MHz HGF LGF = 0 gmM
3V 0 1 10 fxtal (MHz) 10
2
0 1 3 5
3.58 MHz HGF LGF gmL 10.7 MHz HGF = LGF = 0 gmM 3.58 MHz HGF = LGF = 0 gmL VDD (V) 7
Measured with function generator on XTAL1.
Measured with crystal between XTAL1 and XTAL2.
Fig.7
Typical operating supply current (IDD) as a function of clock frequency (fxtal).
Fig.8
Typical supply current in Idle mode (IDD(idle)) as a function of supply voltage (VDD).
1996 Dec 18
29
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
PCD3350A
handbook, halfpage
6
MGB830
MGB784
handbook, halfpage
6
IDD(idle) (mA) 4
IDD(stp) (A) (2) 4
2
5V
2
3V 0 1 10 fxtal (MHz) 10 0
(1)
2
1 1.5
3 3.35
5
VDD (V)
7
Measured with function generator on XTAL1.
(1) RTC stopped; Tamb = -25 to +70 C. (2) RTC running; Tamb = -25 to +70 C.
Fig.9
Typical supply current in Idle mode (IDD(idle)) as a function of clock frequency (fxtal).
Fig.10 Typical supply current in Stop mode (IDD(stp)) as a function of supply voltage (VDD).
MGB831
handbook, halfpage
12
handbook, halfpage
-300
MGB832
IOL (mA) 8
IOH (A) -200
VO = 0 V
4
-100 VO = 0.9VDD
0 1 3 5 VDD (V) 7
0 1 3 5 VDD (V) 7
VO = 0.4 V.
Fig.11 Typical LOW level output sink current (IOL) as a function of supply voltage (VDD).
Fig.12 Typical HIGH level pull-up output source current (IOH) as a function of supply voltage (VDD).
1996 Dec 18
30
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
PCD3350A
handbook, halfpage
-12
MGB833
handbook, halfpage
-18
MGB791
IOH1 (mA) -8
gm (S) Tamb = -14 -25 oC
-4
-10
+25 oC +70 oC
0 1 VO = VDD - 0.4 V. 3 5 VDD (V) 7
6 1 3 5 VDD (V) 7
Fig.13 Typical HIGH level push-pull output source current (IOH1) as a function of supply voltage (VDD).
Fig.14 Typical RTC oscillator transconductance as a function of supply voltage (VDD).
MGD495
handbook, halfpage
handbook, halfpage VDD
6
VDD (V)
4
DEVICE TYPE NUMBER (1) TONE 1 F
50 pF
10 k
VPOR = 2.0 V 2 VPOR = 1.3 V
VSS
MGB835
0 -25
25
75 125 Tamb (C) 70
(1) Device type number: PCD3350A
Fig.15 Tone output test circuit.
Fig.16 Typical Power-on-reset level (VPOR) as function of ambient temperature (Tamb).
1996 Dec 18
31
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
PCD3350A
handbook, halfpage
10
MGB790
gmH gm (mS) gmM 1 gmL
10
1
1
3
5
VDD (V)
7
Fig.17 Typical oscillator transconductance (gm) as a function of supply voltage (VDD).
19 AC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = -25 to +70 C; all voltages with respect to VSS; unless otherwise specified. SYMBOL tr tf fxtal PARAMETER rise time all outputs fall time all outputs clock frequency see Fig.5 CONDITIONS VDD = 5 V; Tamb = 25 C; CL = 50 pF - - 1 MIN. TYP. 30 30 - MAX. - - 16 UNIT ns ns MHz
1996 Dec 18
32
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
20 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
PCD3350A
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1996 Dec 18
33
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
21 SOLDERING 21.1 Introduction
PCD3350A
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 21.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 21.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1996 Dec 18
34
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator, 256 bytes EEPROM and real-time clock
22 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCD3350A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 23 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Dec 18
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417021/1200/04/pp36
Date of release: 1996 Dec 18
Document order number:
9397 750 01028

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